A tracking clock recovery receiver for 4-Gbps signaling

We have previously described a design for a 4Gb/s signaling system that uses transmitter equalization to overcome the frequency-dependent attenuation due to skin effect in transmission lines. We present here experimental results from an implementation of this idea in 0.5μ CMOS, showing the effectiveness of a simple transition-filter equalization technique. Our experimental chips use a tracking clock recovery receiver, in which a 21-phase clock is servoed to center every other clock on the center of the data “eye”. This method is contrasted with the oversampling method of clock recovery. Oversampling clock recovery has the advantage that it can reject jitter up to the lesser of the minimum transition frequency or the data clock frequency, but it introduces quantization jitter of ± 1/2k of the bit cell, where k is the number of samples per cell. Tracking recovery gives better performance when there is little jitter above the cutoff frequency of the tracking control loop, avoids quantization jitter entirely, and allows transmitter encoding with much longer run-lengths. Electrical measurements in very high-speed signaling systems are quite difficult to perform with conventional instrumentation, particularly for on-chip signals; this paper describes our design for simple CMOS analog samplers that enable observation of on-chip signals.